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timing generator for frame readout ccd image sensor description the CXD3605R is a timing generator ic which generates the timing pulses for performing frame readout using the icx406 ccd image sensor. features base oscillation frequency 36mhz high-speed/low-speed shutter function supports draft (octuple speed)/af(auto focus) drive horizontal driver for ccd image sensor vertical driver for ccd image sensor applications digital still cameras structure silicon gate cmos ic applicable ccd image sensors icx406 (type 1/1.8, 3980k pixels) pin configuration absolute maximum ratings supply voltage v dd v ss ?0.3 to +7.0 v v l ?0.0 to v ss v v h v l ?0.3 to +26.0 v input voltage v i v ss ?0.3 to v dd + 0.3 v output voltage v o1 v ss ?0.3 to v dd + 0.3 v v o2 v l ?0.3 to v ss + 0.3 v v o3 v l ?0.3 to v h + 0.3 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd b 3.0 to 5.25 v v dd a, v dd c, v dd d 3.0 to 3.6 v v m 0.0 v v h 14.55 to 15.45 v v l ?.0 to ?.0 v operating temperature topr ?0 to +75 ? ? groups of pins enclosed in the figure indicate sections for which power supply separation is possible. ?1 e00z48 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD3605R 48 pin lqfp (plastic) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 mcko ssi sck sen vd hd v ss 6 h1 v ss 3 v ss 2 rg v dd 2 ssgsl v dd 1 wen id/exp sncsl rst v ss 1 test2 sub v3b vl v3a v1b vh v1a v4 v2 vm test1
2 CXD3605R block diagram 35 34 39 44 43 41 5 4 24 23 22 20 19 21 18 17 16 15 10 9 8 11 13 12 14 28 27 26 25 30 v1b v2 v3a v1a wen id/exp v ss 5 adclk obclp clpdm pblk v ss 4 xrs xshd xshp v dd 4 v ss 2 rg v dd 2 v ss 3 h2 h1 v dd 3 vd hd 7 29 1 v ss 1 36 v ss 6 v dd 5 v dd 1 mcko cko cki osco osci pulse generator 2 37 48 test2 test1 rst 45 38 42 47 40 46 vl vm vh sub v4 v3b 31 32 33 sen sck ssi register v driver 6 ssgsl 3 sncsl 1/2 1/2 selector selector selector latch ssg
3 CXD3605R pin description gnd internal system reset input. high: normal operation, low: reset control normally apply reset during power-on. schmitt trigger input control input used to switch sync system. high: cki sync, low: mcko sync with pull-down resistor vertical direction line identification pulse output/exposure time identification pulse output. switching possible using the serial interface data. (default: id) memory write timing pulse output. internal ssg enable. high: internal ssg valid, low: external sync valid. with pull-down resistor 3.3v power supply. (power supply for common logic block) 3.3v power supply. (power supply for rg) ccd reset gate pulse output. gnd gnd ccd horizontal register clock output. ccd horizontal register clock output. 3.3 to 5.0v power supply. (power supply for h1/h2) 3.3v power supply. (power supply for cds block) ccd precharge level sample-and-hold pulse output. ccd data level sample-and-hold pulse output. sample-and-hold pulse output for analog/digital conversion phase alignment. pulse output for horizontal and vertical blanking period pulse cleaning. ccd dummy signal clamp pulse output. gnd ccd optical black signal clamp pulse output. the horizontal/vertical ob pattern can be changed using the serial interface data. clock output for analog/digital conversion ic. logical phase adjustment possible using the serial interface data. gnd inverter output. inverter input. inverter output for oscillation. when not used, leave open or connect a capacitor. inverter input for oscillation. when not used, fix low. 3.3v power supply. (power supply for common logic block) system clock output for signal processing ic. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ss 1 rst sncsl id/exp wen ssgsl v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 mcko i i o o i o o o o o o o o o o o i o i o pin no. symbol i/o description
4 CXD3605R serial interface data input for internal mode settings. schmitt trigger input serial interface clock input for internal mode settings. schmitt trigger input serial interface strobe input for internal mode settings. schmitt trigger input vertical sync signal input/output. horizontal sync signal input/output. gnd ic test pin 1; normally fixed to gnd. with pull-down resistor gnd (gnd for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ccd vertical register clock output. 15.0v power supply. (power supply for vertical driver) ccd vertical register clock output. ccd vertical register clock output. 7.5v power supply.(power supply for vertical driver) ccd vertical register clock output. ccd electronic shutter pulse output. ic test pin 2; normally fixed to gnd. with pull-down registor 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ssi sck sen vd hd v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 i i i i/o i/o i o o o o o o o i pin no. symbol i/o description
5 CXD3605R electrical characteristics dc characteristics (within the recommended operating conditions) v dd2 v dd3 v dd4 v dd1 , v dd5 rst, ssi, sck, sen test1, test2, sncsl, ssgsl vd, hd h1, h2 rg xshp, xshd, xrs, pblk, obclp, clpdm, adclk cko mcko id/exp, wen v1a, v1b, v3a, v3b, v2, v4 sub v dd a v dd b v dd c v dd d v t+ v t v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 v oh5 v ol5 v oh6 v ol6 v oh7 v ol7 i ol i om1 i om2 i oh i osl i osh 3.0 3.0 3.0 3.0 0.8v dd d 0.7v dd d 0.8v dd d v dd d 0.8 v dd b 0.8 v dd a 0.8 v dd c 0.8 v dd d 0.8 v dd d 0.8 v dd d 0.8 10.0 5.0 5.4 3.3 3.3 3.3 3.3 3.6 5.25 3.6 3.6 0.2v dd d 0.2v dd d 0.2v dd d 0.4 0.4 0.4 0.4 0.4 0.4 0.4 5.0 7.2 4.0 v v v v v v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma feed current where i oh = 1.2ma pull-in current where i ol = 2.4ma feed current where i oh = 22.0ma pull-in current where i ol = 14.4ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 6.9ma pull-in current where i ol = 4.8ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 2.4ma pull-in current where i ol = 4.8ma v1a/b, v2, v3a/b, v4 = 8.25v v1a/b, v2, v3a/b, v4 = 0.25v v1a/b, v3a/b = 0.25v v1a/b, v3a/b = 14.75v sub = 8.25v sub = 14.75v supply voltage 1 supply voltage 2 supply voltage 3 supply voltage 4 input voltage 1 ? 1 input voltage 2 ? 2 input/output voltage output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 output voltage 6 output current 1 output current 2 item pins symbol conditions min. typ. max. unit ? 1 this input pin is a schmitt trigger input. ? 2 this input pin is with pull-down registor in the ic. note) the above table indicates the condition for 3.3v drive.
6 CXD3605R inverter i/o characteristics for oscillation (within the recommended operating conditions) item logical vth input voltage output voltage feedback resistor oscillation frequency pins osci osci osco osci, osco osci, osco symbol lvth v ih v il v oh v ol rfb f conditions feed current where i oh = 3.6ma pull-in current where i ol = 2.4ma v in = v dd d or v ss min. 0.7v dd d v dd d 0.8 500k 20 typ. v dd d/2 2m max. 0.3v dd d 0.4 5m 50 unit v v v v v ? mhz item logical vth input voltage input amplitude pins cki symbol lvth v ih v il v in conditions fmax 50mhz sine wave min. 0.7v dd d 0.3 typ. v dd d/2 max. 0.3v dd d unit v v v vp-p item rise time fall time output noise voltage symbol ttlm ttmh ttlh ttml tthm tthl vclh vcll vcmh vcml conditions vl to vm vm to vh vl to vh vm to vl vh to vm vh to vl min. 200 200 30 200 200 30 typ. 350 350 60 350 350 60 max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 unit ns ns ns ns ns ns v v v v inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) note) input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through a capacitor. switching characteristics (vh = 15.0v, vm = gnd, vl = 7.5v) note) 1) the mos structure of this ic has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) for noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1f or more) between each power supply pin (vh, vl) and gnd. 3) to protect the ccd image sensor, clamp the sub pin output at vh before input to the ccd image sensor.
7 CXD3605R switching waveforms v1a (v1b, v3a, v3b) v2 (v4) sub ttmh tthm vh vm vl vm vl vh vl 90% 10% 90% 10% ttlm ttlm 90% 10% 90% 10% ttlh tthl 90% 90% 10% 10% ttml 90% 10% ttml 90% 10% waveform noise vcmh vcml vm vl vclh vcll
8 CXD3605R measurement circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vd cki c6 c6 c6 c6 c6 c6 c6 c6 c6 c5 c5 c4 c3 CXD3605R serial interface data hd +3.3v 7.5v +15.0v c2 c2 c2 c2 c2 r1 r1 r1 r2 r1 r1 r1 c2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 c1 c2 c1 3300pf c2 560pf c3 820pf c4 8pf c5 215pf c6 10pf r1 30 ? r2 10 ?
9 CXD3605R ac characteristics ac characteristics between the serial interface clocks ssi 0.2v dd d 0.2v dd d 0.8v dd d ts2 th1 ts1 ts3 0.8v dd d 0.8v dd d sck sen sen symbol t s1 t h1 t s2 t s3 definition ssi setup time, activated by the rising edge of sck ssi hold time, activated by the rising edge of sck sck setup time, activated by the rising edge of sen sen setup time, activated by the rising edge of sck min. typ. max. 20 20 20 20 unit ns ns ns ns serial interface clock internal loading characteristics (1) (within the recommended operating conditions) th1 enlarged view example: during frame mode 0.2v dd d ts1 0.2v dd d v1a vd hd hd v1a sen 0.8v dd d symbol t s1 t h1 definition sen setup time, activated by the falling edge of hd sen hold time, activated by the falling edge of hd min. typ. max. 0 110 unit ns s ? be sure to maintain a constantly high sen logic level near the falling edge of the hd in the horizontal period during which v1a/b and v3a/b values take the ternary value and during that horizontal period. (within the recommended operating conditions)
10 CXD3605R serial interface clock output variation characteristics normally, the serial interface data is loaded to the CXD3605R at the timing shown in "serial interface clock internal loading characteristics (1)" above. however, one exception to this is when the data such as stb is loaded to the CXD3605R and controlled at the rising edge of sen. see "description of operation". 0.8v dd d sen output signal tpdpulse symbol tpdpulse definition output signal delay, activated by the rising edge of sen min. typ. max. 100 5 unit ns (within the recommended operating conditions) serial interface clock internal loading characteristics (2) th1 0.2v dd d ts1 0.2v dd d vd hd vd hd sen 0.8v dd d enlarged view example: during frame mode symbol t s1 t h1 definition sen setup time, activated by the falling edge of vd sen hold time, activated by the falling edge of vd min. typ. max. 0 200 unit ns ns ? be sure to maintain a constantly high sen logic level near the falling edge of vd. (within the recommended operating conditions)
11 CXD3605R rst 0.2v dd d tw1 0.8v dd d vd hd ts1 th1 0.2v dd d 0.2v dd d 0.2v dd d rst loading characteristics symbol t w1 definition rst pulse width min. typ. max. 25 unit ns (within the recommended operating conditions) vd and hd phase characteristics symbol t s1 t h1 definition vd setup time, activated by the falling edge of hd vd hold time, activated by the falling edge of hd min. typ. max. 20 100 unit ns ns (within the recommended operating conditions) hd mcko ts1 th1 0.2v dd d 0.8v dd d 0.2v dd d hd loading characteristics symbol t s1 t h1 definition hd setup time, activated by the rising edge of mcko hd hold time, activated by the rising edge of mcko min. typ. max. 20 5 unit ns ns mcko load capacitance = 10pf (within the recommended operating conditions)
12 CXD3605R 0.8v dd d mcko wen, id/exp tpd1 wen and id/exp load capacitance = 10pf (within the recommended operating conditions) symbol tpd1 definition time until the above outputs change after the rise of mcko min. typ. max. 60 20 unit ns output variation characteristics
13 CXD3605R description of operation pulses output from the CXD3605R are controlled mainly by the rst pin and by the serial interface data. the pin status table is shown below, and the details of serial interface control are described on the following pages. pin status table ? 1 it is for output. for input, all items are "act". note) act means that the circuit is operating, and dis means that loading is stopped. l indicates a low output level, and h a high output level in the controlled status. also, vh, vm and vl indicate the voltage levels applied to vh (pin 42), vm (pin 38) and vl (pin 45), respectively, in the controlled status. pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v ss 1 rst sncsl id/exp wen ssgsl v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 act act act act act act act act act act act act act act act act act l l act l l l l l l l l l l act act l l act l l l l l l l l l l l act l l act act act act act act act h h h act 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cko cki osco osci v dd 5 mcko ssi sck sen vd ? 1 hd ? 1 v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 act act act act act act act act act act act act act act act act act act act act act act act act act l l vm vm vh vh vh vh vh l act act act l act act act l l vm vm vh vh vh vh vh act act act act act dis dis dis h h vm vl vm vm vl vl vl symbol cam slp stb rst pin no. symbol cam slp stb rst
14 CXD3605R serial interface control the CXD3605R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of hd. here, readout portion specifies the horizontal period during which v1a/b and v3a/b, etc. take the ternary value. note that some items reflect the serial interface data at the falling edge of vd or the rising edge of sen. ssi sck sen 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 these are two categories of serial interface data: the CXD3605R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). the details of each data are described below.
15 CXD3605R control data data d00 to d07 d08 to d09 d10 to d12 d13 d14 d15 to d16 d17 d18 to d31 d32 d33 d34 to d35 d36 to d37 d38 to d39 d40 to d47 symbol chip ctg mode smd htsg ntpl fgob exp ptob ldad stb function chip enable category switching drive mode switching electronic shutter mode switching ? 1 htsg control switching ? 1 ssg function switching wide obclp generation switching id/exp output switching obclp waveform patterm switching adclk logic phase adjustment standby control data = 0 data = 1 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d12 mode. off on off on ntsc pal off on id exp see d34 to d35 ptob. see d36 to d37 ldad. see d38 to d39 stb. rst all 0 all 0 all 0 0 0 all 0 0 all 0 0 0 all 0 1 0 all 0 all 0 ? 1 see d13 smd.
16 CXD3605R shutter data data d00 to d07 d08 to d09 d10 to d19 d20 to d31 d32 to d41 d42 to d47 symbol chip ctg svd shd spl function chip enable category switching electronic shutter vertical period specification electronic shutter horizontal period specification high-speed shutter position specification data = 0 data = 1 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d19 svd. see d20 to d31 shd. see d32 to d41 spl. rst all 0 all 0 all 0 all 0 all 0 all 0
17 CXD3605R detailed description of each data shared data: d08 to d09 ctg [category] of the data provided to the CXD3605R by the serial interface, the CXD3605R loads d10 and subsequent data to each data register as shown in the table below according to the combination of d08 and d09 . d09 0 0 1 d08 0 1 x description of operation loading to control data register loading to shutter data register test mode d11 0 0 1 1 d12 0 0 0 0 d10 0 1 0 1 d11 0 0 1 1 d12 1 1 1 1 d10 0 1 0 1 description of operation description of operation draft mode (default) af1 mode af2 mode frame mode draft mode frame mode (a field read out) frame mode (b field read out) test mode note that the CXD3605R can apply these categories consecutively within the same vertical period. however, care should be taken as the data is overwritten if the same category is applied. control data: d10 to d12 mode [drive mode] the CXD3605R drive mode can be switched as follows. however, the drive mode bits are located to the CXD3605R and reflected at the falling edge of vd. draft mode is the pulse eliminator drive mode called octuple speed mode in the icx406. this is a high frame rate drive mode that can be used for purposes such as monitoring and auto focus (af). af1 and af2 modes are the pulse eliminator drive modes called by the same names in the icx406. these drive modes are based on draft mode, and are used to increase the frame rate for auto focus (af). in these modes, the screen is swept in the vertical direction and the center portion lines are cut out. frame mode is the icx406 drive mode in which the data for all lines are read. this drive mode is comprised of a and b fields, so when it is established, repeated drive is performed in the manner of a b a and so on. frame mode (a or b field) is the drive mode in which each field can be specified separately. control data: d17 ntpl [ssg function switching] the CXD3605R internal ssg output pattern can be switched as follows. however, the ssg function switching bits are loaded to the CXD3605R and reflected at the falling edge of vd. d17 0 1 description of operation ntsc equivalent pattern output pal equivalent pattern output vd period in each pattern is defined as follows. see the timing charts for the actual operation. ntsc equivalent pattern pal equivalent pattern frame mode 1012h + 1672ck 944h + 464ck draft mode 224h + 1372ck 2 269h + 2039ck af1 mode 112h + 1372ck 134h + 2354ck af2 mode 56h + 686ck 67h + 1178ck
18 CXD3605R control data: d32 fgob [wide obclp generation] this controls wide obclp generation during the vertical opb period. see the timing charts for the actual operation. the default is "off". d32 0 1 description of operation wide obclp generation off wide obclp generation on control data: d34 to d35 ptob [obclp waveform pattern] this indicates the obclp waveform pattern. the default is "normal". d35 0 0 1 1 d34 0 1 0 1 waveform pattern (normal) (shifted rearward) (shifted forward) (wide) control data: d36 to d37 load [adclk logical phase] this indicates the adclk logic phase adjustment data. the default is 90 relative to mcko. d37 0 0 1 1 d36 0 1 0 1 degree of adjustment ( ) 0 90 180 270 control data: d38 to d39 stb [standby] the operating mode is switched as follows. however, the standby bits are loaded to the CXD3605R and control is applied immediately at the rising edge of sen. d39 x 0 1 d38 0 1 1 symbol cam slp stb operating mode normal operating mode sleep mode standby mode see the pin status table for the pin status in each mode.
19 CXD3605R control data/shutter data: [electronic shutter] the CXD3605R realizes various electronic shutter functions by using control data d13 smd and d14 htsg and shutter data d10 to d19 svd, d20 to d31 shd and d32 to d41 spl. these functions are described in detail below. first, the various modes are shown below. these modes are switched using control data d13 smd. d13 0 1 description of operation electronic shutter stopped mode electronic shutter mode the electronic shutter data is expressed as shown in the table below using d20 to d31 shd as an example. however, msb (d31) is a reserve bit for the future specification, and it is handled as a dummy on this ic. msb lsb d29 d28 d31 d30 d27 d26 d25 d24 d23 d22 d21 d20 1100 c x001 1 0011 3 shd is expressed as 1c3h . [electronic shutter stopped mode] during this mode, all shutter data items are invalid. sub is not output in this mode, so the shutter speed is the accumulation time for one field. [electronic shutter mode] during this mode, the shutter data items have the following meanings. note) the bit data definition area is assured in terms of the CXD3605R functions, and does not assure the ccd characteristics. the period during which svd and shd are specified together is the shutter speed. an image of the exposure time calculation formula is shown below. in actual operation, the precise exposure time is calculated from the operating frequency, vd and hd periods, decoding value during the horizontal period, and other factors. (exposure time) = svd + {(number of hd per 1v) (shd + 1)} concretely, when specifying high-speed shutter, svd is set to "000h". (see the figure.) during low-speed shutter, or in other words when svd is set to "001h" or higher, the serial interface data is not loaded until this period is finished. the vertical period indicated here corresponds to one field in each drive mode. in addition, the number of horizontal periods applied to shd can be considered as (number of sub pulses 1). symbol svd shd spl data d10 to d19 d20 to d31 d32 to d41 description number of vertical periods specification (000h svd 3ffh) number of horizontal periods specification (000h shd 7ffh) vertical period specification for high-speed shutter operation (000h spl 3ffh)
20 CXD3605R vd shd 1 v1a sub wen smd 000h 002h svd 050h 10fh shd 1 svd exp exposure time vd spl 001 002 000 shd 1 v1a sub wen smd 000h 001h spl 000h 002h svd 0a3h 10fh shd exp exposure time 1 svd further, spl can be used during this mode to specify the sub output at the desired vertical period during the low-speed shutter period. in the case below, sub is output based on shd at the spl vertical period out of (svd + 1) vertical periods. incidentally, spl is counted as "000h", "001h", "002h" and so on in conformance with svd. using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa.
21 CXD3605R vd v1a sub wen 0 1 0 htsg 1 0 1 smd vck exposure time exp [htsg control mode] this mode controls the v1a/b and v3a/b ternary level outputs (readout pulse block) using d14 htsg. d14 0 1 description of operation readout pulse (sg) normal operation htsg control mode [exp pulse] the id/exp pin (pin 4) output can be switched between the id pulse or the exp pulse using d33 exp. the default is the "id" pulse. see the timing charts for the id pulse. the exp pulse indicates the exposure time when it is high. the transition point is the last sub pulse falling edge, and midpoint value (1338ck) of each v1a/b and v3a/b ternary out put falling edge. when there is no sub pulse, the later ternary output falling edge (1416ck) is used. see the exp pulse indicated in the explanatory diagrams under [electronic shutter] for an image of operation. note that the above specification is based on draft mode. for frame mode, the former value is 1260ck and the latter value is 1416ck.
22 CXD3605R vd sub obclp clpdm v1a c c v1b v2 v3a v3b v4 ccd out 1547 1719 1712 1714 1716 1718 1720 1709 1711 1713 1715 3 1 57 246810 2 12 468 9111357911 pblk id/exp wen a field b field hd 1 75 82 17482 1013 943 943 1013 a b high-speed sweep block high-speed sweep block ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? vd of this chart is ntsc equivalent pattern (1012h + 1672ck units). for pal equivalent pattern, it is 944h + 464ck units. chart-1 vertical direction timing chart mode frame mode applicable ccd image sensor icx406
23 CXD3605R vd hd sub v1a v2 v3a v3b v4 obclp clpdm id/exp pblk v1b ccd out 14 5 10 21 30 37 10 1 6 1 17 26 33 46 42 5 10 14 21 30 37 1 6 1 10 17 26 33 46 42 wen 3 1 218 3 1 218 d d 1717 1710 1713 1706 1717 1710 1713 1706 226 226 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? vd of this chart is ntsc equivalent pattern (224h + 1372ck + 1372ck units). for pal equivalent pattern, it is 269h + 2039ck uni ts. chart-2 vertical direction timing chart mode draft mode applicable ccd image sensor icx406
24 CXD3605R vd sub obclp clpdm v1a v1b v2 v3a v3b v4 ccd out pblk id/exp wen hd 2 9 29 106 106 10 6 10 6 e f g ge f 113 113 high-speed sweep block frame shift block high-speed sweep block frame shift block ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? 240 stages are fixed for high-speed sweep block; 232 stages are fixed for frame shift block. ? vd of this chart is ntsc equivalent pattern (112h + 1372ck units). for pal equivalent pattern, it is 134h + 2354ck units. chart-3 vertical direction timing chart mode af1 mode applicable ccd image sensor icx406
25 CXD3605R vd sub obclp clpdm v1a high-speed sweep block v1b v2 v3a v3b v4 ccd out pblk id/exp wen hd 2 12 212 47 47 10 6 10 6 g g e f e frame shift block high-speed sweep block frame shift block f 57 57 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? 360 stages are fixed for high-speed sweep block; 360 stages are fixed for frame shift block. ? vd of this chart is ntsc equivalent pattern (56h + 686ck units). for pal equivalent pattern, it is 67h + 1178ck units. chart-4 vertical direction timing chart mode af2 mode applicable ccd image sensor icx406
26 CXD3605R hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp (1) obclp (2) obclp (3) obclp (4) obclp clpdm (2669) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 317 345 361 365 60 4 188 92 50 24 42 16 58 16 347 58 58 32 343 319 252 156 220 60 343 60 284 124 232 168 124 124 ? the hd of this chart indicates the actual CXD3605R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. id/exp and wen are output at the timing shown above at the position shown in chart-1. chart-5 horizontal direction timing chart mode frame mode applicable ccd image sensor icx406
27 CXD3605R hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp (1) obclp (2) obclp (3) obclp (4) obclp clpdm (2669) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 317 345 361 365 60 4 92 68 50 24 42 16 58 16 347 58 58 32 343 319 108 84 100 60 343 60 116 76 232 168 124 124 156 132 172 148 164 124 180 140 220 196 212 228 188 244 204 284 260 300 276 292 252 308 268 236 ? the hd of this chart indicates the actual CXD3605R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. id/exp and wen are output at the timing shown above at the position shown in chart-2, 3 and 4. chart-6 horizontal direction timing chart mode draft mode, af1 mode, af2 mode applicable ccd image sensor icx406
28 CXD3605R hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp clpdm (2669) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 317 345 361 365 60 4 116 60 232 168 172 228 284 340 396 452 508 564 116 60 172 228 284 340 396 452 508 564 144 88 200 256 312 368 424 480 536 144 88 200 256 312 368 424 480 536 #4 #3 #2 #1 #5 ? the hd of this chart indicates the actual CXD3605R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. ? high-speed sweep of v1a/b, v2, v3a/b, v4 is performed up to 72h of 2660ck (#1739). chart-7 horizontal direction timing chart (high-speed sweep: c) mode frame mode applicable ccd image sensor icx406
29 CXD3605R hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp clpdm (2669) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 317 345 361 365 60 4 232 168 60 60 50 24 124 100 124 164 188 228 252 292 316 356 380 420 444 484 508 548 108 148 172 212 236 276 300 340 364 404 428 468 492 532 556 84 92 132 156 196 220 260 284 324 348 388 412 452 476 516 540 68 76 116 140 180 204 244 268 308 332 372 396 436 460 500 524 #6 #7 #4 #5 #3 #1 #2 #8 ? the hd of this chart indicates the actual CXD3605R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. pblk, obclp, id/exp and wen are output at the timing shown above at the position shown in chart- 2, 3 and 4. ? frame shift of v1a/b, v2, v3a/b and v4 is performed up to 7h 1563ck (#232) in af1 mode and 10h 1688ck (#360) in af2 mode. in addition, high-speed sweep is performed up to 111h 2015ck (#240) in af1 mode and 55h 1688ck (#360) in af2 mode. chart-8 horizontal direction timing chart (frame shift: f) (high-speed sweep: g) mode af1 mode, af2 mode applicable ccd image sensor icx406
30 CXD3605R hd [a field] [b field] a b v3b v4 v3b v4 v1a v1b v2 v3a v1a v1b v2 v3a (2669) 0 (2669) 0 1104 1136 1168 1200 1202 1260 1292 124 156 188 220 252 284 ? the hd of this chart indicates the actual CXD3605R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. chart-9 horizontal direction timing chart mode frame mode applicable ccd image sensor icx406
31 CXD3605R hd d v3b v4 v1a v1b v2 v3a (2669) 0 (2669) 0 1104 1136 1168 1200 1202 1356 1358 1260 1292 1324 1416 60 76 92 108 124 140 156 172 68 84 100 116 132 148 164 180 ? the hd of this chart indicates the actual CXD3605R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. chart-10 horizontal direction timing chart mode draft mode applicable ccd image sensor icx406
32 CXD3605R hd e v3b v4 v1a v1b v2 v3a (2669) 0 (2669) 0 1104 1136 1168 1200 1202 1356 1358 1260 1292 1324 1416 60 76 92 108 124 140 156 172 68 84 100 116 132 148 164 180 188 204 220 236 252 268 284 300 196 212 228 244 260 276 292 308 1448 1464 1480 1496 1512 1528 1544 1560 1456 1472 1488 1504 1520 1536 1552 1568 ? the hd of this chart indicates the actual CXD3605R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.3 to 17.6s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. chart-11 horizontal direction timing chart mode af1 mode, af2 mode applicable ccd image sensor icx406
33 CXD3605R hd hd' cki cko adclk mcko h1 h2 rg xshp xshd xrs 317 60 1 ? hd' indicates the hd which is the actual CXD3605R load timing. ? the phase relationship of each pulse shows the logical position relationship. for the actual output waveform, a delay is added to each pulse. ? the logical phase of adclk can be specified by the serial interface data. chart-12 high-speed phase timing chart mode applicable ccd image sensor icx406
34 CXD3605R vd v1a v1b v2 v3a v3b v4 sub mechanical shutter exposure time ccd out mode smd shd close open abc ee f 0 0000 3 3 0 0 1 1111 0 0 1 1 050h 050h 050h 050h 050h 000h 000h 050h 050h abcde f ? this chart is a drive timing chart example of electronic shutter normal operation. ? data exposed at d includes the blooming component. for details, see the ccd image sensor data sheet. ? the CXD3605R does not generate the pulse to control mechanical shutter operation. ? the switching timing of drive mode and electronic shutter data is not the same. chart-13 vertical direction sequence chart mode draft frame draft applicable ccd image sensor icx406
35 CXD3605R application circuit block diagram 26 27 37 48 31 32 34 35 30 25 23 22 20 19 18 17 16 mcko vd hd cko d out adclk obclp clpdm pblk xrs xshd xshp sck 33 sen ssi test2 test1 osco cki 28 osci ccd out v-dr ssg 6 3 2 5 4 ssgsl sncsl rst wen id/exp 12 13 9 rg h2 h1 41 43 39 v2 v1b v1a 44 46 40 v4 47 sub v3b v3a ccd icx406 cds/adc block tg CXD3605R controller signal processor block notes for power-on of the three 7.5v, +15.0v, 3.3v power supplies, be sure to start up the 7.5v and +15.0v power supplies in the following order to prevent the sub pin of the ccd image sensor from going to negative potential. t1 t2 15.0v 0v 7.5v 20% 20% t2 t1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
36 CXD3605R sony corporation package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 0.02 + 0.05 a 1.5 0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0 to 10 detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03

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